Some processing apparatuses are provided with multiple storage units for storing data and/or instructions on behalf of a processing circuit. When the processing circuit requests access to a data value (whether a read access for reading the current value of the data value or a write access for writing a new value of the data value), the circuit determines which of the storage units stores the requested data value. Determining which storage unit contains the target data can take several processing cycles, and so waiting for the target storage unit to be determined before initiating the read or write access can slow down processing performance.
For faster performance, some processing apparatuses can predict which of the storage units contains the target data, and initiate access to the predicted storage unit before it has been determined which storage unit actually stores the target data. Hence, it is not necessary to wait for the actual determination of the target storage unit before the data access can be initiated. The prediction may be made in dependence on part of the target storage address of the access request. The present technique seeks to provide an efficient way of predicting which storage unit stores the target data.